It is known to reduce a design rule for semiconductor fabrication to increase the density of integrated circuits. It is further known to reduce the design rule for multi-layered wiring in semiconductor devices. When wiring has a multi-layered structure, a contact may be needed to electrically connect between layers. It is known to use polysilicon for a barrier metal layer and a contact plug in such applications. However, to reduce a resistance of a contact plug and also to employ a metal-insulator-metal (MIM) type capacitor in the semiconductor device, the polysilicon plug may need to be replaced with a metal plug.
It is known to form a barrier layer, including a titanium layer and a titanium nitride layer stacked thereon, on inner sides of a contact hole. The barrier layer is then thermally treated to form a titanium silicide layer. Tungsten is deposited on the barrier layer by a chemical vapor deposition (CVD) process to form a tungsten wiring.
The titanium silicide layer may reduce the contact resistance of a semiconductor device. However, as a junction depth becomes shallow due to a high degree of integration of the semiconductor device, a leakage current from the titanium siclide layer may increase.
To overcome the above-mentioned problems, a conventional method of forming a tungsten silicide layer is disclosed in Korean Patent Laid Open Publication No. 1998-60526. FIGS. 1A to 1C are cross sectional views illustrating the conventional method discussed in the above Korean Patent Laid Open Publication.
Referring to FIG. 1A, an insulation layer (not shown) is formed on a semiconductor substrate 10. The insulation layer is partially etched to form an insulation layer pattern 20 having a contact hole 25 that partially exposes the substrate 10. The substrate 10 is then cleaned to remove particles or etch residues in the contact hole 25. A preliminary tungsten nitride layer 30 having a thickness of about 50 Å to about 1,000 Å is formed on the insulation layer pattern 20 and the contact hole 25 by a CVD process.
Referring to FIG. 1B, a tungsten layer 40 is formed on the preliminary tungsten nitride layer 30 to fill the contact hole 25.
Referring to FIG. 1C, the substrate 10 is thermally treated at a temperature of about 600° C. to about 900° C. to form a tungsten silicide layer 32 and a tungsten nitride layer 34 between the substrate 10 and a portion of the tungsten layer 40 in the contact hole 25.
The tungsten layer 40 is then etched by a dry etching process to form tungsten wiring (not shown) in the contact hole 25. The tungsten wiring may reduce a contact resistance and also may reduce/prevent an increase of a leakage current.
As shown in FIG. 6, after the tungsten layer 40 is etched, a recess R having a deep depth is formed at an upper portion of the tungsten wiring, thereby causing a contact failure of a semiconductor device. In addition, the conventional tungsten wiring may be formed at a relatively high temperature. Thus, a thermal stress due to the deposition process at a high temperature may be generated in a pattern on the substrate 10 so that the pattern may be thermally damaged.